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HM-6561/883
March 1997
256 x 4 CMOS RAM
Description
The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On-chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The data inputs and outputs are multiplexed internally for common I/O bus compatibility. The HM-6561/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Low Power Standby . . . . . . . . . . . . . . . . . . . . 50W Max * Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max * Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 200ns Max * Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min * TTL Compatible Input/Output * High Output Drive - 1 TTL Load * On-Chip Address Registers * Common Data In/Out * Three-State Output * Easy Microprocessor Interfacing
Ordering Information
PACKAGE TEMPERATURE RANGE CERDIP -55oC to +125oC 220ns HM1-6561B/883 300ns HM1-6561/883 PKG. NO. F18.3
Pinout
HM-6561/883 (CERDIP) TOP VIEW
A3 A2 A1 A0 A5 A6 A7 GND E 1 2 3 4 5 6 7 8 9 18 VCC 17 A4 16 W 15 S1 14 DQ3 13 DQ2 12 DQ1 11 DQ0 10 S2
PIN A E W S DQ
DESCRIPTION Address Input Chip Enable Write Enable Chip Select Data In/Out
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2990.1
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HM-6561/883 Functional Diagram
A0 A1 A5 A6 A7 A LATCHED ADDRESS REGISTER 5 A 5 L G A D DQ0 A Q LATCH L D DQ1 A Q LATCH L D DQ2 A Q LATCH L D DQ3 A Q LATCH L A L W E A2 S1 S2 A3 A4 3 A 3 A A A GATED COLUMN DECODER AND DATA I / O G 8 8 8 8 GATED ROW DECODER 32 x 32 MATRIX
32
LATCHED ADDRESS REGISTER
NOTES: 1. All lines positive logic-active high. 2. Three-state Buffers: A high output active. 3. Data Latches: L high Q = D and Q latches on falling edge of L. 4. Address Latches and Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
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HM-6561/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage. . . . . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance JA JC CERDIP Package . . . . . . . . . . . . . . . . 74oC/W 18oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . VCC - 2.0V to VCC Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
TABLE 1. HM-6561/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER Output Low Voltage SYMBOL VOL (NOTE 1) CONDITIONS VCC = 4.5V, IOL = 1.6mA VCC = 4.5V, IOH = -0.4mA VCC = 5.5V, VI = GND or VCC VCC = 5.5V, VIO = GND or VCC VCC = 2.0V, E = VCC, IO = 0mA, VCC = 5.5V, (Note 2), E = 1MHz, W = GND, VI = VCC or GND VCC = 5.5V, IO = 0mA, VI = VCC or GND GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN MAX 0.4 UNITS V
Output High Voltage
VOH
1, 2, 3
2.4
-
V
Input Leakage Current
II
1, 2, 3
-1.0
+1.0
A A
Input/Output Leakage Current
IIOZ
1, 2, 3
-1.0
+1.0
Data Retention Supply Current
ICCDR
1, 2, 3
-55oC TA +125oC
-
10
A
Operating Supply Current
ICCOP
1, 2, 3
-55oC TA +125oC
-
4
mA
Standby Supply Current
ICCSB
1, 2, 3
-55oC TA +125oC
-
10
A
NOTES: 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP.
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HM-6561/883
TABLE 2. HM-6561/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested
LIMITS
PARAMETER Chip Enable Access Time Address Access Time Chip Select Output Enable Time Chip Select Output Disable Time Chip Enable Pulse Negative Width Chip Enable Pulse Positive Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Data Delay Time Chip Select Write Pulse Setup Time Chip Enable Write Pulse Setup Time Chip Select Write Pulse Hold Time Chip Enable Write Pulse Hold Time Write Enable Pulse Width Read or Write Cycle Time
SYMBOL (1) TELQV (2) TAVQV (3) TSLQX
(NOTES 1, 2) CONDITIONS
VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V, (Note 3) VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V
GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11
HM-6561B/883 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 5 MAX 220 220 -
HM-6561/883 MIN 5 MAX 300 300 UNITS ns ns ns
(4) TSHQZ
9, 10, 11
-55oC TA +125oC
-
120
-
150
ns
(5) TELEH (6) TEHEL (7) TAVEL (8) TELAX (9) TDVWH (10) TWHDX (11) TWLDV (12) TWLSH (13) TWLEH (14) TSLWH (15) TELWH (16) TWLWH (17) TELEL
9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
-55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
220 100 0 40 100 0 20 120 120 120 120 120 320
-
300 100 0 50 150 0 30 180 180 180 180 180 400
-
ns ns ns ns ns ns
ns ns ns ns ns ns
NOTES: 1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: IOL = 1.6mA, IOH = -0.4mA, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 3. TAVQV = TELQV + TAVEL.
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HM-6561/883
TABLE 3. HM-6561/883 ELECTRICAL PERFORMANCE SPECIFICATIONS LIMITS SYMBOL CI PARAMETER Input Capacitance CONDITIONS VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground NOTE 1 TEMPERATURE TA = +25oC MIN MAX 8 UNITS pF
CO
Output Capacitance
1
TA = +25oC
-
10
pF
NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process and/or design changes. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
Test Load Circuit
DUT (NOTE 1) CL
IOH
+ -
1.5V
IOL
EQUIVALENT CIRCUIT
NOTE: 1. Test head capacitance includes stray and jig capacitance.
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HM-6561/883 Timing Waveforms
(7) TAVEL A (8) TELAX VALID (17) TELEL (6) TEHEL E W HIGH (1) TELQV (2) TAVQV HIGH Z DQ PREVIOUS DATA (4) TSHQZ S1, S2 (4) TSLQX VALID DATA LATCHED (4) TSHQZ HIGH Z (5) TELEH (6) TEHEL (7) TAVEL
TIME REFERENCE -1 0 1 2 3 4 5
FIGURE 1. READ CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 5 H L L E H S1 H X L L L H X W X H H H H X H A X V X X X X V OUTPUT DQ Z Z X V V Z Z Memory Disabled Cycle Begins, Addresses are Latched Output Enabled Output Valid Output Latched Device Disabled, Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION
NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.
The HM-6561/883 Read Cycle is initiated on the falling edge of E. This signal latches the input address word into on-chip registers. Minimum address setup and hold times must be met. After the required hold time, the address lines may change state without affecting device operation. In order to read the output data E, S1 and S2 must be low and W must be high. The output data will be valid at access time (TELQV).
The HM-6561/883 has output data latches that are controlled by E. On the rising edge of E the present data is latched and remains latched until E falls. Either or both S1 or S2 may be used to force the output buffers into a high impedance state.
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HM-6561/883 Timing Waveforms (Continued)
(7) TAVEL A (8) TELAX VALID (17) TELEL (6) TEHEL E (13) TWLEH (15) TELWH W (11) TWLDV DQ (16) TWLWH (9) TDVWH VALID DATA (14) TSLWH (12) TWLSH S1, S2 TIME REFERENCE -1 0 1 2 3 4 5 (10) TWHDX (5) TELEH (6) TEHEL (7) TAVEL NEXT
FIGURE 2. WRITE CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 5 H L L E H S1 H X L L X H X H X X W X X L A X V X X X X V DQ X X X V X X X Memory Disabled Cycle Begins, Addresses are Latched Write Period Begins Data In is Written Write is Completed Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION
NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.
The write cycle begins with the E falling edge latching the address. The write portion of the cycle is defined by E, S1, S2 and W all being low simultaneously. The write portion of the cycle is terminated by the first rising edge of any control line, E, S1, S2 or W. The data setup and data hold times (TDVWH and TWHDX) must be referenced to the terminating signal. For example, if S2 rises first, data setup and hold times become TDVS2H and TS2HDX; and are numerically equal to TDVWH and TWHDX. Data input/output multiplexing is controlled by W. Care must be taken to avoid data bus conflicts, where the RAM outputs become enabled when another device is driving the data inputs. The following two examples illustrate the timing required to avoid bus conflicts.
Case 1: Both S1 and S2 Fall Before W Falls. If both selects fall before W falls, the RAM outputs will become enabled. W is used to disable the outputs, so a disable time (TWLQZ = TWLDV) must pass before any other device can begin to drive the data inputs. This method of operation requires a wider write pulse, because TWLDV + TDVWH is greater than TWLWH. In this case TWLSL + TSHWH are meaningless and can be ignored. Case 2: W Falls Before Both S1 and S2 Fall. If one or both selects are high until W falls, the outputs are guaranteed not to enable at the beginning of the cycle. This eliminates the concern for data bus conflicts and simplifies data input timing. Data input may be applied as early as convenient, and TWLDV is ignored. Since W is not used to disable the outputs it can be shorter than in Case 1; TWLWH
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HM-6561/883
is the minimum write pulse. At the end of the write period, if W rises before either select the outputs will enable reading data just written. They will not disable until either select goes high (TSHQZ).
IF CASE 1 Both S1 and S2 = Low Before W = Low OBSERVE TWLQZ TWLDV TDVWH TWLWH TDVWH IGNORE TWLWH
If a series of consecutive write cycles are to be performed, W may remain low until all desired locations are written. This is an extension of Case 2. Read-Modify-Write cycles and Read-Write-Read cycles can be performed (extension of Case 1). In fact data may be modified as many times as desired with E remaining low.
CASE 2
W = Low Before Both S1 and S2 = Low
TWLQZ TWLDV
Burn-In Circuit
HM-6561/883 CERDIP
VCC F6 F5 F4 F3 F8 F9 F10 1 2 3 4 5 6 7 8 F0 9 A3 A2 A1 A0 A5 A6 A7 GND E VCC 18 A4 17 W 16 S1 15 DQ3 14 DQ2 13 DQ1 12 DQ0 11 S2 10 F7 F1 F0 F2 F2 F2 F2 F0 C1
NOTES: All resistors 47k 5%. F0 = 100kHz 10%. F1 = F0 / 2, F2 = F1 / 2, F3 = F2 / 2 . . . F12 = F11 / 2. VCC = 5.5V 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V. C1 = 0.01F Min.
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HM-6561/883 Die Characteristics
DIE DIMENSIONS: 132 x 160 x 19 1mils METALLIZATION: Type: Si - Al Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1.337 x 105 A/cm2 LEAD TEMPERATURE (10s soldering): 300oC
Metallization Mask Layout
HM-6561/883
S1 W DQ3 DQ2 DQ1 DQ0
S2
A4
VCC A3
A2
E A1 A0 A5 A6 A7 GND
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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